Semiconductor Intelligence · Founded 2024

Every wafer tells
a story. We teach
fabs to read it.

Anvaya is an AI platform that turns wafer defect maps, process sensor data, and fab telemetry into real-time yield intelligence — closing the gap between what a fab produces and what it could.

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1%
Yield gain = $100M+ per fab line
700+
Process steps per wafer
3 nm
Feature sizes driving zero-tolerance defect regimes
$600B
Global semiconductor market by 2030
The Problem

Modern fabs generate petabytes of data
and act on almost none of it.

Advanced chip manufacturing involves over 700 sequential process steps, each generating sensor readings, metrology measurements, and defect inspection images. By the time a wafer reaches final test, actionable signals from step 47 are long buried under noise.

Conventional statistical process control (SPC) catches drift after the damage is done. Root-cause analysis is still largely manual — engineers spending weeks correlating defect maps to process excursions. Meanwhile, every failed wafer at an advanced node represents $10,000–$50,000 in sunk cost.

The problem compounds across the supply chain: a yield excursion at one fab disrupts allocation across every downstream customer, with no intelligent rebalancing layer to absorb the shock.

~40%
Of yield loss is attributable to systematic, correctable process variation — detectable before the wafer reaches final test.
Live Wafer Defect Map · Lot 4472
Pass Marginal Fail
AI scan active · Cluster defect detected · Step 284 correlation pending
The Platform

Four modules.
One connected intelligence layer.

01
YieldSight
Predictive yield modeling from multi-layer wafer defect maps. Spatial deep learning identifies killer defect clusters, predicts final yield distribution, and flags lots at risk — hours before electrical test, not after.
Yield Prediction Engine
02
ProcessARC
Closed-loop automated process control using reinforcement learning. Continuously correlates equipment sensor data with inline metrology to propose — and with customer approval, execute — compensatory recipe adjustments before drift becomes excursion.
Automated Process Control
03
DesignGuard
AI-accelerated design rule checking (DRC) that goes beyond geometric verification. DesignGuard learns process-specific printability margins from historical SEM data, flagging design patterns statistically likely to yield fail — before tape-out.
Design Rule Intelligence
04
FabFlow
Intelligent supply chain allocation across multi-fab networks. When a yield excursion occurs at one node, FabFlow rebalances wafer starts, prioritizes customer commits by margin, and surfaces reallocation options — in real time.
Supply Chain Intelligence
How It Works

From raw fab data
to prescriptive action

01
Ingest & Unify
Anvaya connects to existing fab data infrastructure — KLA, Applied Materials, ASML inspection systems, MES platforms, and equipment OPC-UA endpoints — via a zero-disruption integration layer. No rip-and-replace.
// Data connectors · SEMI standards · SECS/GEM · KIF
02
Model & Learn
Spatial graph neural networks map defect cluster morphology to process signatures. Contrastive learning across historical lot data surfaces non-obvious correlations between step-N events and step-N+200 yield outcomes. Models are fab-specific and continuously updated.
// GNN · Contrastive learning · Causal inference · Time-series
03
Predict & Prescribe
Every lot receives a live yield forecast updated at each inspection point. When risk crosses a threshold, Anvaya surfaces the most probable root cause, the corrective action with highest expected yield recovery, and the confidence interval — so engineers decide with full context, not instinct.
// Explainable AI · Uncertainty quantification · Root cause scoring
04
Act & Close the Loop
Approved interventions — recipe tweaks, lot holds, reallocation decisions — flow back through ProcessARC and FabFlow into the control system. Outcomes feed back into the model. The fab gets measurably smarter with every wafer processed.
// Closed-loop APC · RLHF-style feedback · Continuous improvement
Market Opportunity

A trillion-dollar industry
running on yesterday's tools.

$18B
Semiconductor Process Control TAM
Global market for yield management, APC, and fab analytics software — growing 14% annually as node complexity scales.
$200B+
Annual yield loss across the industry
Estimated cost of defect-driven yield loss globally. Even recovering 5% of this through better AI represents a $10B opportunity.
40+
Advanced logic & memory fabs worldwide
Each representing a flagship deployment opportunity — with dozens of mature-node fabs providing an accessible beachhead.
The Founder
AB
Amit Bhartiya
Founder & CEO · Anvaya

Amit built Anvaya from a single conviction: that semiconductor manufacturing is the most data-rich industry on earth, and also one of the least data-driven in its decision-making. Having spent years at the intersection of process engineering and machine learning, he saw firsthand how yield engineers made billion-dollar decisions from incomplete information — and how much systematic signal was being discarded at every step.

Anvaya is his answer to that gap. Not a dashboarding tool, not another SPC add-on — but a full inference layer that treats the fab as a learning system. Amit's thesis is that the next competitive frontier in semiconductors isn't lithography equipment or EUV access. It's who turns process data into compounding yield advantage faster.

Deep background in semiconductor process physics and ML systems applied to manufacturing
Operational experience inside advanced logic fabs — understands what yield engineers actually need on the floor
Built Anvaya's core defect-map modeling engine from first principles, validated on real wafer data
Engaging foundries and IDMs across the US and Asia for pilot programs in 2025
Get In Touch

Ready to see what your wafer data has been trying to tell you?

We're working with a select group of fabs and IDMs on early access pilots. If you run yield engineering at an advanced node, we'd like to talk.

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